1. Field of the Invention
The present invention relates to a magneto-sensitive integrated circuit such as a Hall IC (integrated circuit) for outputting an electric signal in response to an applied magnetic field.
2. Description of the Related Background Art
If a magnetic field is generated in a direction passing through the principal plane of a Hall element by flowing a current (or applying a voltage) between the input terminals of the Hall element, electrons within the element are bent in the travel direction owing to a Lorenz's force, so that a potential VH occurs between the output terminals. This phenomenon is called a Hall effect, and the potential VH is called a Hall voltage. The Hall voltage VH can be represented by the following expression.VH=K*I*B  (1)
In this way, the Hall element can produce a voltage proportional to a control current I and a magnetic flux density B of the applied magnetic field. Where K is a Hall element intrinsic value, which is different with the material or shape. The Hall IC is an element in which a Hall element, an amplifier for amplifying the output voltage of the Hall element, and an A/D converter for converting the output voltage of the amplifier into a digital signal are formed in one package, and usable for a contactless switch, rotation detection, position detection and so on.
An offset voltage VOS that is one of the basic characteristics of the Hall element is a voltage occurring between the output terminals only by flowing a current (or applying a voltage) between the input terminals when there is no magnetic field. That is, a sum of the offset voltage VOS and the Hall voltage VH is outputted as a Hall element output voltage VOUT between the output terminals of the Hall element when measuring the magnetic field.
Referring to FIG. 1, a principle of generating the offset voltage VOS will be described below. An equivalent circuit of the Hall element can be represented by a resistor bridge circuit as shown in FIG. 1. A Hall element output voltage VOUT that occurs between the VP-VN terminals when an input voltage Vin is applied between the Vin-Vs terminals in a state with no magnetic field isVOUT=VOS={R4/(R1+R4)−R3/(R2+R3)}*Vin  (2).
If all the resistance values R1 to R4 of four elements forming the bridge are equal, VOUT=0. That is, in this case, the offset voltage VOS is 0. On the other hand, if the resistance values of R1 to R3 are r, and only the resistance value of R4 is r+a, the above expression (2) is solved such that,VOUT=VOS=[a/(4r+2a)]*Vin  (3)whereby the output voltage is generated, irrespective of no magnetic field. That is, the resistance values of four elements making up the bridge are dispersed due to the manufacturing reason, in which its unbalance causes an offset voltage. The offset voltage VOS is almost equal to or more than the Hall voltage VH to be measured, whereby it is required to remove the offset voltage to obtain a correct signal according to the intensity of magnetic field.
A spinning current method, which is known as a method for removing the offset voltage, will be described below. The spinning current method is characterized by producing an output signal according to the intensity of magnetic field through the two step operation including a first step of applying a voltage between the A-A′ terminals of the Hall element and measuring a Hall element output voltage VOUT1 occurring between the B-B′ terminals, and a second step of applying a voltage between the B-B′ terminals and measuring a Hall element output voltage VOUT2 occurring between the A-A′ terminals, as shown in FIGS. 2A and 2B. That is, the spinning current method is a measurement method for producing the Hall element output voltage by exchanging an input terminal pair and an output terminal pair between the first step and the second step. Herein, if the resistance values of R1 to R3 are r and only the resistance value of R4 is r+a, an offset voltage VOS1 occurring at the first step is,VOS1=[a/(4r+2a)]*Vin  (4)from the above expressions (2) and (3). Since the Hall element output voltage VOUT1 occurring between the output terminals B-B′ is the sum of the Hall voltage VH and the offset voltage VOS1,VOUT1=VH+[a/(4r+2a)]*Vin  (5)occurs between the output terminals B-B′ at the first step. On the other hand, an offset voltage VOS2 occurring at the second step isVOS2=[R1/(R1+R2)−R4/(R3+R4)]*Vin=−[a/(4r+2a)]*Vin  (6).Since the Hall element output voltage VOUT2 occurring between the output terminals A-A′ is the sum of the Hall voltage VH and the offset voltage VOS2,VOUT2=VH−[a/(4r+2a)]*Vin  (7)occurs between the output terminals A-A′ at the second step. The Hall element output voltages VOUT1 and VOUT2 obtained at the first and second steps are stored in memory at the timings T1 and T2, respectively. And an adder circuit performs the addition of VOUT1+VOUT2, the result being obtained as the final output. That is, if VOUT1 and VOUT2 are added, 2VH is obtained from the expressions (6) and (7), whereby an output signal containing no offset voltage component can be obtained (refer to Japanese Patent Laid-Open No. 2001-337147 and Japanese Patent Publication No. 6-103341).
A Hall IC has an amplifier for amplifying the Hall element output voltage and an A/D converter for converting the amplifier output into a digital signal, in addition to a Hall element. FIG. 3 is a view showing the relationship between a Hall voltage and an A/D conversion effective area. To improve an A/D conversion precision of the A/D converter, it is required to increase a gain of the amplifier. Herein, since an input voltage of the A/D converter is required to be within an effective area where the A/D converter can perform the processing, it is required that the gain of the amplifier is set taking this into consideration. However, if the output voltage of the Hall element is amplified by the amplifier, not only the Hall voltage VH but also the offset voltage VOS are amplified, so that the gain of the amplifier can not be fully increased. As a result, the A/D conversion precision was not ensured, whereby it was difficult to achieve the sufficient magnetic field detection precision.